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FB REF FS
Phase Freq. DET
Filter
VCO and Time Unit Generator
3F1 4F0
5 6 7 8 9 10 11 12 13
3F0 FS VCCQ REF GND TEST 2F1
4 3 2 1 32 31 30 29 28 27
1F0 1F1
1Q0 1Q1
VCCN FB VCCN 2Q1 2Q0
3Q1 3Q0
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PI6C39911
3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock(R)
Features
* All output pair skew <100ps typical (250 Max.) * 12.5 MHz to 133 MHz output operation * 3.125 MHz to 133 MHz input operation (input as low as 3.125 MHz for 4x operation, or 6.25 MHz for 2x operation) * User-selectable output functions -- Selectable skew to 18ns -- Inverted and non-inverted -- Operation at 1/2 and 1/4 input frequency -- Operation at 2X and 4X input frequency * Zero input-to-output delay * 50% duty-cycle outputs * Inputs are 5V Tolerant * LVTTL outputs drive 50-Ohm terminated lines * Operates from a single 3.3V supply * Low operating current * 32-pin PLCC package * Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50-Ohms while delivering minimal and specified output skews and full-swing logic levels. Each output can be hardwired to one of nine skews or function configurations. Delay increments of 0.7ns to 1.5ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal "zero" skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. The user can create output-to-output skew of up to 12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature allows flexibility and simplifies system timing distribution design for complex high-speed systems.
Logic Block Diagram
Test
Pin Configuration
4F0 4F1
Select Inputs (three level)
4Q0 4Q1 Skew Select Matrix 3Q0 3Q1 2Q0 2Q1
3F0 3F1 2F0 2F1
4F1 VCCQ VCCN 4Q1 4Q0 GND GND
32 Pin J
2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND GND
26 25 24 23 22 21
14 15 16 17 18 19
20
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Pin Descriptions
Signal Name REF FB FS 1F0, 1F1 2F 0, 2F 1 3F 0, 3F 1 4F 0, 4F 1 TEST 1Q0, 1Q1 2Q 0, 2Q 1 3Q 0, 3Q 1 4Q 0, 4Q 1 VCCN VCCQ GND I/O I I I I I I I I O O O O De s cription Reference frequency input supplies the frequency and timing against which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs) Three- level frequency range select. see Table 1. Three- level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2. Three- level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2. Three- level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2. Three- level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2. Three- level select. See test mode section under the block diagram descriptions Output pair 1. see Table 2 Output pair 2. see Table 2 Output pair 3. see Table 2 Output pair 4. see Table 2
PWR Power supply for output drivers PWR Power supply for internal circuitry PWR Ground
Table 1. Frequency Range Select and tU Calculation(1)
FS(1,2) LOW MID HIGH FNOM (M Hz) M in. 12.5 25 40 M a x. 30 50 13 3 tU =
Table 2. Programmable Skew Configurations(1)
Function Se le cts 1F1, 2F1, 3F1, 4F1 LOW LOW LOW MID MID MID HIGH HIGH HIGH 1F0, 2F0, 3F0, 4F0 LOW MID HIGH LOW MID HIGH LOW MID HIGH Output Functions 1Q0, 1Q1, 2Q0, 2Q1 -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU 3Q0, 3Q1 4Q0, 4Q1
1 fNOM x N
whe re N= 44 26 16
Approximate Fre q. (M Hz) at which tU = 1.0ns 22.7 38.5 62.5
Divide by 2 Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Divide by 4 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Inverted
Notes: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the "normal" operating frequency (fNOM) and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input.
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t0 +1tU
t0 +2tU
t0 +3tU
t0 +4tU
t0 +5tU
1Fx 2Fx (N/A) LL LM LH ML MM MH HL HM HH
FB Input REF Input 3Fx 4Fx LM -6tU LH (N/A) ML (N/A) MM (N/A) MH (N/A) HL -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU
(N/A) HM +6tU (N/A) LL/HH Divided (N/A) HH Invert
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output(3) Note: 3. FB connected to an output selected for "zero" skew (i.e., xF1 = xF0 = MID)
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t0 +6tU
t0 -6tU
t0 -5tU
t0 -4tU
t0 -3tU
t0 -2tU
t0 -1tU
t0
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C39911 to operate as explained briefly above (for testing purposes, any of the three level inputs can have a removable jumper to ground, or be tied LOW through a 100 Ohm resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.
Maximum Ratings
Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied ............................................... -55C to +125C Supply Voltage to Ground Potential ................ -0.5V to +5.0V DC Input Voltage .............................................. -0.5V to +5.0V Output Current into Outputs (LOW) .............................. 64mA Static Discharge Voltage ............................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ......................................................... >200mA Maximum Power Dissipation at TA=85C(2,3) .............. 0.80watts
Operating Range
Range Commercial Industrial Ambie nt Te mpe rature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10%
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Capacitance(6)
Parame te r CIN De s cription Input Capacitance Te s t Conditions TA = 25C, f = 1MHz, VCC = 3.3V M ax. 10 Units pF
Electrical Characteristics (Over the Operating Range)
Parame te r VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL IOS ICCQ ICCN PD De s cription Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three- Level Input HIGH Voltage (Test, FS, xFn)(4) Three- Level Input MID Voltage (Test, FS, xFn)(4) Three- Level Input LOW Voltage (Test, FS, xFn)(4) Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS, xFn) Input MID Current (Test, FS, xFn) Input LOW Current (Test, FS, xFn) Short Circuit Current
(5)
Te s t Conditions VCC = Min., IOH = -18mA VCC = Min., IOL = 35mA
M in. 2.4
M a x. 0.45
Units
2.0 -0.5 Min. VCC Max. Min. VCC Max. Min. VCC Max. VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = Max., VOUT = GND (25C only) VCCN = VCCQ = Max., All Input Selects Open Com'l Mil/Ind -50 -200 -20 0.87 VCC 0.47 VCC 0.0
VCC 0.8 V VCC 0.53 VCC 0.13 VCC 20
A 200 50 -200 95 100 19 104 mW mA
Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair Power Dissipation per Output Pair
VCCN = VCCQ = Max., IOUT = 0mA All Input Selects Open, fMAX VCCN = VCCQ = Max., IOUT = 0mA All Input Selects Open, fMAX
Notes: 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 7. Test measurement levels for the PI6C39911 are 1.5V to 1.5V. Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 8. Guaranteed by statistical correlation.
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Switching Characteristics (Over the Operating Range)(2,7)
Parame te r O perating C lock F requency in MHz D e s cription F S = LO W(1 , 2 ) F S = M ID
(1 , 2 ) (1 , 2 )
PI6C39911-2 M in. 12.5 25 40 3.0 3.0 S ee Table 1 0.1 0.20 0.4 0.6 0.4 0.5 0.25 0.25 0.5 0.8 0.5 0.8 1.0 -0.3 -1.0
(1 6 )
PI6C39911-5 Typ. M ax. 30 50 133 12.5 25 40 3.0 3.0 S ee Table 1 0.1 0.25 0.6 0.5 0.5 0.5 0.25 0.5 0.7 1.0 0.7 1.0 1.25 -0.5 -1.0 0.0 0.0 +0.5 +1.0 2.5 3.0 0.15 0.15 1.0 1.0 1.5 1.5 0.5 25 200
Typ. M ax. M in. 30 50 133
Units M in. Typ. M ax. 12.5 25 40 3.0 3.0 S ee Table 1 0.1 0.3 0.6 1.0 0.7 1.2 0.25 0.75 1.0 1.5 1.2 1.7 1.65 -0.7 -1.2 0.0 0.0 +0.7 +1.2 3.0 3.5 0.15 0.15 1.0 1.0 1.5 1.5 0.5 25 200 ms ps ns 30 50 133 ns MHz
PI6C39911
fN O M
(1 , 2 )
F S = HIGH
tR P W H tR P W L tU tS K E W P R tS K E W 0 tS K E W 1 tS K E W 2 tS K E W 3 tS K E W 4 tD E V tP D tO D C V tP W H tP W L tO R I S E tO F A L L tL O C K tJ R
REF P ulse Width HIGH REF P ulse Width LO W P rogrammable S kew Unit Zero O utput Matched - P air S kew (XQ 0, XQ 1)(9 , 1 0 ) Zero O utput S kew (All O utputs)(9 , 11 ) O utput S kew (Rise- Rise, F all- F all, S ame C lass O utputs)(9 , 1 3 ) O utput S kew (Rise- F all, N ominal- Inverted, Divided- Divided)(9 , 1 3 ) O utput S kew (Rise- Rise, F all- F all, Different C lass O utputs)(9 , 1 3 ) O utput S kew (Rise- F all, N ominal- Divided, Divided- Inverted)(9 , 1 3 ) Device- to- Device S kew
(8 , 1 4 )
P ropagation Delay, REF Rise to F B Rise O utput Duty C ycle Variation
(1 5 )
0.0 0.0
+0.3 +1.0 2.5 3.0
O utput HIGH Time Deviation from 50%(1 6 ) O utput LO W Time Deviation from 50% O utput Rise Time O utput F all Time P LL Lock Time C ycle- to- cycle O utput Jitter
(1 6 , 1 7 ) (1 6 , 1 7 )
0.15 0.15 RMS
(8 ) (8 )
1.0 1.0
1.5 1.5 0.5 25 200
(1 8 )
P e a k - to - p e a k
Notes: 9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50 ohms to VCC/2. 10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns. 13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 16. Specified with outputs loaded with 30pF for the PI6C39911 devices. Devices are terminated through 50 Ohm to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 17. tORISE and tOFALL measured between 0.8V and 2.0V. 18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
AC Test Loads and Waveforms
TTL AC Test Load
VCC
TTL Input Test Waveform
R1
1ns 3.0V 2.0V Vth =1.5V 0.8V 0V
1ns
CL
R2
R1=100 R2=100 CL=30pF (Includes fixture and probe capacitance)
AC Timing Diagrams
tREF tRPWH tRPWL
REF
tPD tODCV tODCV
FB
tJR
Q
tSKEWPR tSKEW0, 1 tSKEWPR tSKEW0, 1
Other Q
tSKEW2 tSKEW2
Inverted Q
tSKEW3,4 tSKEW3,4 tSKEW3,4
REF Divided by 2
tSKEW1,3,4 tSKEW2,4
REF Divided by 4
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Operational Mode Descriptions
REF
PI6C39911
PI6C39911
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
FB System Clock REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 Z0 L4 LOAD L3 Z0 LOAD L2 Z0 L1 Z0 LOAD LOAD
LENGTH: L1 = L2 = L3 = L4
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the SUPERCLOCK configured as a zero-skew clock buffer. In this mode the PI6C39911 can be used as the basis for a lowskew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design.
REF
FB System Clock REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 Z0 L4 LOAD L3 Z0 LOAD L2 Z0 L1 Z0 LOAD LOAD
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure 3. Programmable Skew Clock Driver
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PI6C39911
PI6C39911
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the SuperClock can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. Clock skews can be advanced by 6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since "Zero Skew", +tU, and -tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by proper selection of the xFn inputs. For example a +10 tU between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at -4 tU and 3Qx skews to +6 tU , a total of +10 tU skew is realized). Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs.
Figure 4 shows an example of the invert function of the SuperClock. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the "inverted" outputs with respect to the REF input. By selecting which output is connect to FB, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inver-sion on 4Q.
REF FB
20 MHz
REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
80 MHz 4Qx 40 MHz 20 MHz
REF
FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
Figure 5. Frequency Multiplier with Skew Connections Figure 5 illustrates the SuperClock configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which results in a 40 MHz waveform at these outputs. Note that the rising edges of 4Qx and 3Qx outputs are aligned. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output.
Figure 4. Inverted Output Connections
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PI6C39911
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
REF FB
20 MHz
REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
20 MHz 5 MHz 10 MHz
Figure 6. Frequency Divider Connections Figure 6 demonstrates the SuperClock in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the rising edges of the 4Qx and 3Qx outputs are aligned. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency output is running at 20 MHz. Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that
offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different sub-systems on opposite edges, without suffering from the pulse asymmetry typical of nonideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew specification. The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the "1X" clock. Without this feature, an external divider would need to be add-ed, and the propagation delay of the divider would add to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, allow the SuperClock to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a lowfrequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. The SuperClock can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.
REF FB 27.5 MHz Distribution Clock REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
110 MHz Skewed -2.273ns (-4tU) 110 MHz Zero Skew 110 MHz Inverted
LOAD Z0
LOAD 27.5 MHz Z0
LOAD Z0
Z0
LOAD
Figure 7. Multi-Function Clock Driver
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PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
REF LOAD System Clock FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST
FB
L1
4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
Z0
LOAD
L2
Z0
L3
LOAD Z0
L4
Z0
REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
LOAD
LOAD
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the PI6C39911 connected in series to construct a zero skew clock distribution tree between boards. Delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero-
delay clock tree. Cascaded clock buffers will accumulate low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series.
10
PS8497E
09/13/02
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C39911 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Packaging Mechanical: 32-Pin PLCC (J32)
Ordering Information
Accuracy (ps ) Orde ring Code Package Name Package Type Ope rating Range The ta JA (in s till air) (de gre e s C/Watt) The ta JC (de gre e s C/Watt)
250 500 750
PI6C39911- 2J PI6C39911- 5J PI6C39911J J32
32- Pin Plastic Leaded Chip Carrier
Commercial
52
23
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
11
PS8497E 09/13/02

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